This invention relates to the fabrication of semiconductor devices, and, more particularly, to the deposition of dielectric during the fabrication.
Fabrication of semiconductor devices, especially integrated silicon circuits, generally involves deposition of layers of dielectric (e.g., silicon dioxide) on non-silicon surfaces of the in-process device. Frequently, other materials such as metals, polysilicon, etc. will be deposited upon this layer of dielectric. Commonly, plasma enhanced chemical vapor deposition (PECVD) is used to deposit the dielectric.
Problems arise, however, when the dielectric must be deposited on non-planar portions of the in-process device; for example, when metallization must be covered. Indeed, the PECVD of silicon dioxide on a rectangular step leads to a "bread loafed" deposition topography with the silicon dioxide forming an overhead and self-shadowing deposition at the base of the step (see FIG. 1 for a schematic cross sectional view). Various solutions to the poor topography of PECVD have been proposed and include PSG Reflow where the dielectric is chosen to be phosphosilicate glass (PSG). The PSG is deposited in any convenient fashion, and the deposited layer (together with the in-process device) is heated to about 1000.degree. C. which causes the PSG layer to flow and thereby smooth out any poor topography. See, for example, J. Vossen et al., 11 J. Vac. Sci. Tech. 60 (1974) where PSG Reflow and other methods of topography smoothing are considered. The problems with PSG Reflow include the high reflow temperature which may affect other components of the in-process device such as doped aluminum, and the migration of phosphorous out of the PSG during the high temperature reflow affects doping levels in adjacent materials. Use of higher phosphorous content PSG will lower the reflow temperature, but this will lead to metal corrosion problems for any metallization adjacent to the PSG.
Another approach to smooth topography is spin on glass. Various glasses are available in solution at room temperatures and can be spun onto an in-process device and used as the dielectric. After spin on, baking and densification steps are required, but even the densified glass has poor dielectric properties.
A further approach to smooth topography appears in Adams and Capio, Planarization of Phosphorous-doped Silicon Dioxide, 128 J. Electrochem. Soc. 423 (1981). This approach is initially the same as PSG Reflow, in that a dielectric layer is deposited and then a smoothing step follows. But rather than heating the dielectric to reflow as with PSG Reflow, a photoresist is spun onto the in-process device and forms a smooth surface. Following this spin on and curing of the photoresist, an etchant is applied which will etch the photoresist and the dielectric at approximately the same rate, thus the smooth surface of the photoresist, in effect, propagates down until no photoresist or non-smooth dielectric remains. The etching may be done by means of a CF.sub.4 -O.sub.2 plasma and avoids the high temperature that PSG Reflow requires. This process works well, but the multiple steps required limits its practicality.
Bias sputtering of quartz provides another resolution to the topography problem. As described in C. Ting et al., Study of Planarized Sputter-deposited SiO.sub.2, 15 J. Vac. Sci. Tech. 1105 (1978), sputter deposition of quartz together with simultaneous back sputter of the deposited quartz in an Argon RF plasma can lead to a smooth topography of the deposited quartz. The smoothness results from the angular dependence of the back sputtering rate: see FIG. 2 which is a graph of the removal rate by back sputtering as a function of the angle between the normal to the quartz surface being removed and the direction of the incident ions (e.g., Argon) from the plasma. See, M. Nobes et al., 4 J. Mat. Sci. 730 (1969). By varying the split of RF power between the quartz target (deposition sputtering) and the substrate (back sputtering), the contours of the deposited quartz surface can be controlled. However, such bias sputtering has problems including a low deposition rate and target purity. The deposition rate is limited by the heat dissipation capacity of the quartz target.
Thus, there is a problem in the prior art in that a simple (single step) high deposition rate method of depositing dielectrics such as silicon dioxide with smooth topography and high purity is not available.